1. Field of the Invention
The present invention relates to a recording apparatus having a plurality of integrated drive circuits (hereinafter referred to as drive ICs) on the order of several tens and having a plurality of recording elements corresponding to the length of a single line on which information is recorded, and specifically to a recording apparatus categorized in a line-type recording apparatus in which clock signal lines of drive ICs are connected in a cascade configuration.
In addition, the present invention is preferable for forming an ink jet recording apparatus and a thermal printer, used as an output terminal for a word processor, a facsimile, a copying machine, a computer and the like, having heat generation elements used as recording elements.
2. Description of the Background Art
In the prior art, many kinds of line-type recording apparatuses are known which comprise a linear array of a plurality of recording elements. The line-type recording apparatus has several tens of pieces of drive ICs on an identical board, which can generally drive a block of several tens of recording elements simultaneously. With respect to the installation of the drive ICs on the board, a method is known in which drive control signal lines for transmitting image data signals to be supplied to the drive ICs are connected to the first block to the final block of the drive ICs in cascade.
FIG. 1 shows a circuit structure of the line-type recording apparatus in the prior art described above, and FIG. 2 is a detailed structure of the inside of the drive IC enclosed by broken lines in FIG. 1. A reference numeral 1 designates a recording element, to which a recording current is led in response to individual image data signals. A reference numeral 4 denotes a shift register, in which serial image data (SI) corresponding to a single line of recording elements are shifted sequentially with a transfer clock (SCKI). After the transfer of the image data, the image data are loaded into latch circuits 3 by a latch input (LATI) that triggers the latch circuits 3. So far, the image data are prepared for individual recording elements 1.
Now that the image data are prepared for the individual recording elements 1, recording currents are supplied to designated recording elements by activating gate circuits 2. In general, it is necessary to determine electric current supply conditions by considering the characteristics of the recording elements 1 and the recording apparatus itself. With respect to the recording elements 1, the pulse width of each supplied current is so determined that an optimal condition for current supply may be established when supplying the electric current. With respect to the recording apparatus, there is a method in which the recording elements are driven by group in order to distribute the power load applied to the recording elements. A reference numeral 22 in FIGS. 1 and 2 denotes a D-type flip-flop circuit which enables to drive the recording elements by group, each group corresponding to an individual drive IC, in response to the group drive signal (EI) and the group drive signal transfer clock (ECKI). The logical AND of the pulse width (BEI) of electric current supplied to the recording element 1 and the output of the D-type flip-flop circuit 22 is obtained by a gate circuit 21 and an optimal recording current to the recording element is supplied through the gate circuit 21.
In order to increase the image recording speed, the frequency of the image data signal transfer clock (SCKI) for transferring serial image data corresponding to the number of the recording elements 1 is generally determined to be several MHz or more.
So far, by connecting drive control signal lines of drive ICs in cascade, a recording apparatus can be formed with a large number of recording elements, such as several thousand recording elements, arranged in a long single line.
However, in the prior art described above, a recording apparatus with a long-sized array of recording elements, which is formed by connecting drive control signal lines of drive ICs in cascade, requires the clock duty of the input and output waveforms that may change on the order of several nano-seconds, especially when a drive IC is used whose image data signal transfer clock frequency is about 10 MHz. In addition, as the waveforms of input and output signals are susceptible to stray capacitance developed by wiring between the drive ICs, the clock duty of the input and output signals is gradually shifted to the "High" level or to the "Low" level in response to the characteristic of the drive ICs.
For example, assuming to form a recording apparatus having a long-sized array of recording heads for recording images on a A3-sized sheet with a resolution of 400 dpi, it is required to connect 74 drive ICs in cascade, each drive IC corresponding to a block of 64 recording elements. In such a recording apparatus, in the case where the clock duty of the image data signal transfer clock changes gradually, the waveform of the clock signal observed near the final stage of drive ICs may eventually be shifted and fixed at the "High" level or the "Low" level, which leads to failure of correct transmission of the image data.
FIGS. 3 to 6 illustrate switching waveforms of the serial image data (SI) and the image data signal transfer clock (SCKI) in order to illustrate the clock duty change in these signals. FIG. 3 shows a relationship between the image data SI and the clock signal SCKI of the shift register 4 in the drive IC, where "n" is the number of recording elements. When the clock signal SCKI is applied to the logic terminal of the drive IC, as shown in FIG. 4, the waveform of the output signal lengthens by the rise time tr and the fall time tf with respect to its original input signal. The circuit structure of the shift register 4 of the drive IC is shown in FIG. 2, where the clock signal SCKI is outputted through a couple of inverters. In the event that the threshold level at which the clock signal SCKI changes from Lower-level to Higher-level is, for example, between 2.1 V and 2.4 V which is less than 1/2 V.sub.DD, the clock duty at High-level gradually increases as shown in FIG. 5. The details of this phenomenon will be described below.
In FIG. 5, VT is a threshold level corresponding to a single IC, and its value is assumed as follows:
VT&lt;1/2 V.sub.DD, and
V.sub.DD =5.0.
When the clock signal SCKI-1 of the No. 1 drive IC changes from Low-level to High-level, the level of the clock signal SCKO-1 of the No. 1 drive IC begins to increase at the time when the level of the clock signal SCKI-1 reaches V.sub.T. The time period required for the clock signal SCKO-1 of the No. 1 drive IC to change from Low-level to High-level, or from High-level to Low-level corresponds to the tr and tf (see FIG. 4) defined in the standard value of the drive IC. Similarly, when the level of SCKO-1 of the No. 1 drive IC reaches V.sub.T, the level of SCKO-2 of the No. 2 drive IC begins to increase.
As discussed above, as the input waveform of the clock signal SCKI travels through the drive ICs connected in series, the duration during which the High-level signal is maintained lengthens, and hence the waveform of SCKI may be fixed at High-level. In the case where the waveform of SCKI is fixed at High-level completely, since data can not be shifted (sampled) until the next leading edge is developed, there may be failures in printing images such as a black noisy stripe is overlapped on the original image and even the whole recording area is painted in black. Thus, due to the phenomenon in which the input waveform of the clock signal SCKI changes while traveling through the drive ICs connected in series, the image data SI can not be shifted at the leading edge of the clock signal SCKI as shown in FIG. 6.
In order to solve the above problem, in the prior art recording apparatus having a long-sized recording head, the state in which the image data can not be transferred due to the clock duty change is avoided by dividing the input image data and the input image data transfer clock into two components, respectively, or by configuring only clock wiring in parallel. In either case, the cost of the recording apparatus formed in the above manner is relatively high because an increasing number of input terminals and conductive layers formed on the board is required.